Superlattice nanopatterning of wires and complex patterns

ABSTRACT

Fabrication of metallic or non-metallic wires with nanometer widths and nanometer separation distances without the use of lithography. Wires are created in a two-step process involving forming the wires at the desired dimensions and transferring them to a planar substrate. The dimensions and separation of the wires are determined by the thicknesses of alternating layers of different materials that are in the form of a superlattice. Wires are created by evaporating the desired material onto the superlattice that has been selectively etched to provide height contrast between layers. The wires thus formed upon one set of superlattice layers are then transferred to a substrate.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. application Ser. No.10/521,714, filed Jan. 19, 2005 (now U.S. Pat. No. 7,161,168), andclaims priority to PCT Application No. PCT/US03/23546 filed Jul. 28,2003, and U.S. Provisional Application No. 60/399,594, filed Jul. 30,2002, the entire contents of which are incorporated herein by reference.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

This invention was made with support from the Defense Advanced ResearchProjects Agency (DARPA) Grant #MDA972-01-3-0005. The government hascertain rights in this invention.

The U.S. Government has a paid-up license in this invention and theright in limited circumstances to require the patent owner to licenseothers on reasonable terms as provided for by the terms of ARO fundingunder Grant No. MDA972-01-3-0005.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention involves the production of electronic andmechanical devices with length scales measured in nanometers to microns.More particularly, the invention encompasses complicated electricalcircuits, mechanical devices, and spatially modulated physicalproperties. Currently, similar devices (with larger feature sizes) arefabricated using photolithography and related processes often employedby the semiconductor industry.

2. Description of Related Art

The silicon integrated circuit industry (IC) has dominated electronicsand has helped it grow to become one of the world's largest and mostcritical industries over the past thirty-five years. However, because ofa combination of physical and economic reasons, the miniaturization thathas accompanied the growth of Si IC's is reaching its limit. The presentscale of devices is on the order of tenths of micrometers. New solutionsare being proposed to take electronics to even smaller levels; suchsolutions are directed to constructing nanometer scale devices.

Prior proposed solutions to the problem of constructing nanometer scaledevices have involved (1) utilization of extremely fine scalelithography using X-rays, electrons, ions, or scanning probes to definethe device components; (2) direct writing of the device components byelectrons, ions, or scanning probes, or (3) using a master fabricatedwith either process (1) or (2) to stamp the device components into aconformal layer. The major problem with (1) is the capital expensenecessary to build equipment capable of fabricating devices on thenanometer lengthscale. The properties of light at these length scalesrequire expensive optical components, as well as precision translationstages and alignment equipment. Indeed, some components necessary toproduce 30 nm photolithographic structures have not even been inventedyet. While (2) avoids some of these obstacles by using charged particlesinstead of light, the processing is inherently serial. Writing a waferfull of complex devices, each containing trillions of components, couldwell require many years. Process (3) is an alternative to conventionallithography, using a master stamp to imprint a pattern into a film, suchas polymethyl(methacrylate). As currently practiced, however, so-callednano-imprinting is still dependent upon photo- or e-beam lithography todefine the master stamp. Processes (1-3) are all limited with respect tothe density of features that can be patterned. While very smallstructures (wires and discs), with a smallest dimension of 10 to 20nanometers, can be patterned using various of the above techniques, itis very difficult to fabricate such small structures at a high density.The distance that separates the individual structures, known as the‘pitch’ is typically limited to about 60 nanometers or greater. Theinvention described in detail below generates extremely well-definedconducting nanowires, and at densities that are well-beyond the currentstate-of-the-art. The invention may be utilized within the stampingmotif of Process (3), however with a non-lithographically defined masterthat allows much smaller features to be produced.

A related, but distinctly different approach has been described by Chen& Williams (U.S. Pat. No. 6,407,443 “Nanoscale Patterning for theFormation of Extensive Wires,”). In their approach, a differentiallyetched silicon germanium superlattice is utilized as a stamp to producenanoscale wire patterns in a polymer mold. Subsequent processing stepsare then utilized to develop the wires into conducting materials. Thesubsequent processing steps, such as polymer removal, pattern etching,and metal deposition are very difficult to control at nanoscaledimensions, and so it is very difficult to transfer the atomic-levelcontrol that is realized in the superlattice structure into the finalpattern of nanostructures. In the current invention, the nanowires aredeposited directly onto the superlattice, and then transferred, as ifthey were an ink, onto the substrate, without any additional processing.This allows for the full atomic fidelity of the superlattice to beutilized. In many applications, such as those that require themechanical or chemical properties of the nanowires, small variations innanowire structure can lead to large variations in mechanical orchemical properties. The present invention uniquely avoids such physicalproperties variations in the nanowires.

There remains a need for a basic approach to form nanometer-scaledevices that can be used to form more complex circuits and systems, andthat scale readily and inexpensively down to nanometer scale dimensions.

SUMMARY OF THE INVENTION

The invention detailed below uniquely addresses the problems encounteredin current efforts to fabricate devices with features on the nanometerlength-scale by translating the difficulty of defining nanometer lateralspatial dimensions to a problem of controlling the thicknesses ofalternating thin films.

The invention is based upon a structure of alternating thin film layers,known as a superlattice, to define lateral feature sizes. Here after, wewill label the superlattice nanopatterning (SNAP) of wires and complexpatterns as the SNAP process. An example of a superlattice is a stack ofGaAs/AlxGa1-xAs (0.5<x<1) layers, deposited by molecular beam epitaxy(MBE) or metallorganic chemical vapor phase deposition (MOCVD) onto asuitable substrate, with atomic monolayer thickness control. The methoddescribed below is not limited to a particular superlattice. Anystructure of alternating layers of non-identical materials (metals,semiconductors, compound semiconductors, ceramic, insulators or organiclayers) can serve as a superlattice template for this process. To defineuseful lateral features based on the superlattice template, a smallamount of one layer of the superlattice is selectively removed from thepolished cross section of the superlattice. The alternating layerheights thus created then serve as the lateral template. In particular,deposition of material selectively onto one layer allows for theformation of nanowires that are at the width and separation that isdetermined by the superlattice spacings. Such spacings can be controlleddown to atomic dimensions. Material selectively deposited onto thesuperlattice can be subsequently transferred to a substrate by simplecontact and release processing, as described below, and this is the mainfeature of the present invention.

In accordance with the present invention, a superlattice is providedthat includes a template portion. The template portion is composed of aplurality of parallel channels wherein each of the channels includes twochannel sidewalls that each have an upper edge and a lower edge. Thechannels each further include a channel bottom that extends between thelower edge of the channel sidewalls. The channel sidewalls and channelbottom form a plurality of trenches. The template portion furtherincludes a plurality of top surfaces that extend between the upper edgesof the channel sidewalls of adjacent channels. The top surfaces formplateaus or mesas that are located between the channels. The topsurfaces and channel sidewalls are composed of a material that isdifferent from the channel bottom.

As one feature of the present invention, one or more wire-formingmaterials are applied to the template portion of the superlattice toform coatings that cover only the top surfaces. These coatings can thenbe transferred as wires of material to a suitable substrate. Theinvention also covers applying one or more wire-forming materials to thetemplate portion in such a way that the resulting coating covers onlythe top surfaces and a portion of the channel sidewalls. In thisembodiment, angular shaped wires of material are formed that aresuitable for transfer to a substrate. The wire-forming material can alsobe applied to the template portion so that only the channel bottoms andpossibly a portion of the channel sidewalls are covered with material.

This technique to form nanometer scale features has several advantagesover traditional approaches. First, the difficulty of defining nanometerscale patterns using photolithography due to the fundamental physicalproperties of light and electron beams are completely avoided, as thereis little problem producing superlattices with arbitrary thick (or thin)layers and periodicity. In addition, the extremely expensive fabricationfacilities required for nanometer photolithography are not needed, asthe precise positioning tools and special optics required forphotolithography at these scales are obviated. Second, unlike e-beamlithography or ion-milling, the superlattice approach is not serial, andcan be performed repeatedly to form complex patterns. For massproduction purposes, the superlattice process can be applied to form a‘master,’ in another material if desired (for additional toughness forinstance), to template very complicated structures in one step. Third,the superlattice technique can be used to directly deposit fully formedmetallic wires, without the lift-off processing steps used in bothphoto- and e-beam lithography. This is an important advantage, ascomplete removal of excess metal in the lift-off step is a verychallenging for nanometer features, often causing complete loss of thedevice and lowering overall yields.

Fourth, using ion beam with a fine probe diameter (7-10 nm), thesuperlattice template can be shaped to form a SNAP master stamp withvery complex geometries.

Finally, the actual wires and wire assemblies that can be produced usingthis technique have intrinsic characteristics that arise from theirnanoscale dimensions and/or their ultra-high densities. Thesecharacteristics involve both the mechanical and chemical properties ofthe individual nanowires, as well as the collective mechanical andchemical properties of the nanowire assemblies.

The above discussed and many other features and attendant advantages ofthe present invention will become better understood by reference to thedetailed description when taken in conjunction with the accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a process flow diagram for the use of the superlattice as aphysico-chemical template.

FIG. 2 is a process flow diagram for the superlattice wire depositiontechnique detailed herein.

FIG. 3 is a process flow diagram for the use of the superlattice as aphysical template.

FIG. 4 a is a scanning electron microscopy (SEM) image of a GaAs/AlGaAssuperlattice after selective etching of the AlGaAs layers, viewed fromabove. The lattices shown are composed of mesas and trenches withdimensions of 5/15, 10/20, 20/40 nm respectively.

FIG. 4 b is a SEM image of the same lattice, but viewed from the side toshow the profile of the GaAs and AlGaAs layers after etching.

FIG. 5 a is an SEM image of a set of Pt wires deposited with thetechnique described below, demonstrating the uniformity and qualitypossible with this method. The gradings of mesas and trenches shown are50/60, 30/50, 20/40 and 10/20 nm, (note that not as many periods arevisible in this figure) respectively.

FIG. 5 b is a higher magnification SEM image highlighting the quality ofthe 10 nm wide Pt wires at 30 nm pitch. The two sets of wires are 20/40and 10/20 nm spacing.

FIG. 5 c is a higher magnification SEM image highlighting the quality oftwenty 8 nm wide Pt wires at 16 nm pitch.

FIG. 6 a shows a crossbar assembled by sequential deposition of two setsof Pt wires at 90° to one another. Notice the high fidelity of thewires, and the multiple length scales this technique can address at onetime. The lattices shown have the same wires and spaces as in FIG. 3 a.

FIG. 6 b is a higher magnification SEM image of FIG. 5 a, that shows thealignment that is possible at 60 nm pitch in accordance with the presentinvention. The wires are 20 nm wide, with 40 nm gaps.

FIG. 7 is an SEM image of a set of forty 20 nm wide single crystalsilicon wires patterned at a pitch of 60 nm, and twenty 20 nm wide wirespatterned at a pitch of 30 nm. These wires were created by using thedeposited metal wires as an etch mask. The wires were deposited onto a50 nm thick single-crystal silicon-on-insulator film, and the excesssilicon between the metal wires was removed by plasma etching.

FIG. 8 shows wires created in accordance with the present inventionsuspended over a trench.

FIG. 9 a details use of the superlattice patterning technique to producefeatures in a photoresist-type material using the physical imprint ofthe superlattice, similar to FIG. 3.

FIG. 9 b demonstrates a technique to use near-field optical exposure ofphotoresist through a superlattice mask to define features smaller thanthe light wavelengths inherent diffraction limit.

DETAILED DESCRIPTION OF THE INVENTION Definitions

A ‘superlattice’ is defined as a stack of alternating layers ofnon-identical materials. This includes, but is not exclusive to,semiconductors, metals, insulators, organic and ceramics. Thesuperlattice may have several different types or composition of layers,with a minimum of two.

A ‘master’ is a pattern or template that is used repeatedly to patternother surfaces. A rubber stamp is an example of a master, used torepeatedly transfer an ink pattern to a paper substrate.

Thicknesses of GaAs/Al_(x)Ga1-_(x)As (0.5<x<1) layers are labeled asxx/yy nm, denoting xx nm wide GaAs layers alternating with yy nm wideAlGaAs layers. The same notation will be used for the width of thedeposited wires and the spaces in between. Thus, 10/20 nm Pt wiresdenotes 10 nm wide Pt wires with 20 nm space between each wire, for atotal center-to-center distance of 30 nm. The ‘pitch’ of a set of wiresis then defined as the center-to-center distance of each wire.

Superlattice Templating

The SNAP processing method is based on the idea of using the physicallyand chemically distinct layers of a superlattice to define a spatialtemplate or pattern that can be ‘developed’ by selectively depositingnanowires onto one component of the superlattice. The nanowires may thenbe transferred to virtually any substrate. This approach is quite uniquefrom all other approaches to define nanometer to micron scale patterns,which ultimately rely upon light or energetic particles to definefeatures. Techniques such as e-beam lithography or ion beam milling bothuse a collimated beam of electrons or ions to produce patterns, and arewritten serially. Photolithography relies upon a mask fabricated bylaser ablation, photo- or e-beam lithography to selectively block lightfrom a photoresist layer. The SNAP processing method avoids all theproximity effects that are inherent to the previously mentionedlithography techniques. Consequently, the use of a superlattice as aphysical or chemical template is unique, and can produce much smallerfeatures that are more closely spaced than any other lithographic methodcurrently available. Another unique feature associated with the SNAPprocess is the obtention of very sharp angles between nano patternedfeatures. This is again due to the absence of proximity effects found inconventional lithography processes.

Several exemplary methods that use the superlattice templating techniquein accordance with the present invention are described herein. Themethods are based upon the differentiation provided by the alternatingphysical and chemical properties of the superlattice. First, the sharpchemical differentiation between selectively etched superlattice layers,designated A and B in FIG. 1, can direct self-assembly or attachment ofchemical or biological species, which are very sensitive to the localchemical potentials. For instance, after selectively etching layer B(AlGaAs), nanoparticles coated with alkylthiols will attach solely tothe top of the GaAs layers (layer A), forming strings or lines ofnanoparticles with well-defined spaces in between, see FIG. 1. If thespecies to be attached preferentially binds to the etched layer, thespacing of the superlattice can serve as a size-selective filter, onlyallowing species smaller than the layer thickness to deposit. Bysynthesizing several different superlattices, this technique may allowsize selective separation of a variety of species.

Secondly, the superlattice can be used to template wires with sizes andpitches in the nanometer size range. Using the method described here, wehave made gratings of trenches and mesa wires with periodity as small as1 nm/2 nm. This method utilizes simple physical transfer of fully formedwires from a selectively etched superlattice onto an appropriatesubstrate. The wires are formed by evaporating metal (or other material)directly upon one layer of the superlattice, after selective removal ofthe other layer(s) to create trenches. By depositing the metal solelyupon one superlattice layer, the wire widths are defined by thethicknesses of these layers, and conversely the separation between thewires by the thicknesses of the other layers. Thus, the lateral wiredimensions are controlled by the film thicknesses of the superlattice.Well-defined wires can be readily fabricated down to 8 nm widths or lessin this manner. A schematic flow diagram for this process is depicted inFIG. 2.

To form the wires, often of metal, a given material is selectivelyevaporated onto the top of the GaAs layers by tilting the superlatticewith respect to the evaporative flux. This declination allows theevaporated material to be deposited only upon the GaAs layers, due totheir relative elevation to the etched AlGaAs layers. FIG. 2 shows asketch of the incident flux onto a tilted wafer, clearly showing how thematerial deposits onto only one superlattice layer. Any material thatcan be deposited directionally may be used with this technique. Thisincludes, but is not exclusive to: metals, semiconductor compounds,ceramics, and organics. Gold, chromium, aluminum, platinum, titanium,niobium, bismuth, and nickel wires have all been demonstrated. Otherorganic materials, such as pentacene wires, have been demonstrated usingthis technique. In addition, the functionality of the deposited wirescan be enhanced by evaporating multiple materials upon the samesubstrate, forming poly-metallic or composite wires. For example,bismuth/platinum and bismuth/chromium multi-layered wires have beendemonstrated. These multiple-layer wires may have additional usesbesides conductive wires, such as rectifying, sensing, thermoelectric,mechanical resonator, or chemical applications.

The wires evaporated onto the superlattice are transferred to a planarsubstrate by contacting the coated superlattice to an adhesive layer onthe substrate, as illustrated in FIG. 2. Several variants of thisprocess can be used. The adhesive layer can range widely—includingpolymers, pre-polymers, epoxies, or molecular films. In some cases, anadhesive layer may not be necessary, relying instead on electronic,thermodynamic, or van der Waals forces to attach the wires to thesubstrate. The substrate material is also high variable, and, in somecases, is not even necessary. The superlattice typically does not needto contact the substrate surface directly, rather only to make uniformcontact with the adhesive layer. The substrate requirements aretherefore predicated upon the thickness of the adhesive layer—generallythe surface roughness of the substrate must be less than the thicknessof the adhesive layer. The substrate surface chemistry may vary widelyas well, so long as it maintains good adhesion with the material used asthe adhesive layer. This enables use of non-conventional substrates suchas plastics, ceramics, metals, or organics. The use of a substrate couldalso be avoided entirely by using curable adhesives, such as epoxy orpre-polymers, to encapsulate the wires directly.

Physically contacting the superlattice sample to the adhesive layer maybe carried out with a number of techniques. It is only required that thesuperlattice makes even contact with the adhesive layer with some amountof pressure. The manner in which this is performed can varysubstantially. The simplest method is to place the superlattice on topof the substrate, and let its own weight create conformal contact.Application of pressure to the superlattice at this point can provideadditional control over the bonding between the wires and the adhesivelayer. Sophisticated alignment and contact devices, such asnano-imprinters, wafer bonders, photomask aligners and ball presses canall be used to modify this basic step to achieve slightly enhancedcontact between the superlattice and the substrate.

At this point, the wires must be released from the superlattice. Therelease technique also has a number of variants, depending upon theexact materials used. For the GaAs/AlGaAs superlattices, a diluteGaAsO_(x) etch will remove the oxidized surface layer on the GaAslayers, freeing the metal wires. Bi-metallic wires can also be used,with the first layer serving as a sacrificial layer which is etched torelease the other layers. In this manner the original superlattice iscompletely unharmed by multiple wire depositions, and can be usedrepeatedly. If the original superlattice is structurally damaged duringthis process, it may be polished according to standard procedures, andthen re-used. If the wires have poor adhesion to the superlattice, arelease etch may be completely unnecessary. Subsequent processing may beperformed on the deposited wires, however at this point they are readyfor use.

Useful post-processing includes using the wires as etch masks to etchinto the substrate, as shown in the final step of FIG. 2. Complicatedstructures, crystalline and crystallographically aligned materials,polycrystalline materials or thick films that would not normally bepossible to deposit onto a superlattice, as described above, may bepatterned by growing these materials onto a substrate, and etched usingthe superlattice wire process as a mask. This is particularly useful formaterials that cannot be directionally deposited, such as single-crystalsilicon. Etching the pattern provided by these wires into a substrate isperformed with common practices in the semi-conductor industry, such aswet-chemical or plasma etching. Other useful post-processing stepsinclude using selective etch processes to remove the adhesive layer,which may be an undesirable material for the final application. Forexample, if the final application requires that additional materials bedeposited or additional features be patterned, this is often accompaniedby thermal treatment of the wafer. In such cases, an organic epoxy ormolecular film adhesive layer may contaminate these subsequent steps,thus is removed, e.g. by O₂ plasma etching. Another usefulpost-processing step is to suspend the wires. In this way the wires arefree to move or vibrate, and may serve as useful mechanical devices suchas resonators.

Finally, the well-defined, square edges and trenches of the selectivelyetched superlattices serve as robust physical templates. Such nanometerscale physical gratings are useful for a number of applications, such asstandards for scanning probe microscopy, or diffraction gratings for UVto X-ray wavelength light. The superlattices can also be used as masterstamps for techniques such as nano-imprinting, or form molds using softmatter, such as PDMS. An illustration of this technique is shown in FIG.3. We have demonstrated nano-imprinting into epoxy resins using thesuperlattice described above, and believe that it can be readilytransferred to other conformal materials as well.

Reduction to Practice: Nanoscale Metal and Semiconductor Wires

As an example of the reduction to practice of this technique, we detailthe fabrication of wires and circuits made of metal or silicon usingGaAs/Al_(0.8)Ga_(0.2)As superlattices. Atomic level control over thethickness and composition of each layer was achieved by synthesizingsome GaAs/AlGaAs superlattices via molecular beam epitaxy (MBE). Onesuperlattice was composed of 5 sets of different layer thickness: 50/60,30/50, 20/40, 10/20, and 5/15 nm GaAs/Al_(x)Ga_(1-x)As (0.5<x<1) widths,respectively. Each set is composed of eight GaAs layers, which becomethe templates for the metal wires. 300 nm GaAs buffer layers were grownbetween each set of layers to provide isolation. These buffer layers arenot essential, demonstrated by its omission between the 50/60 and 30/50nm sets. A second superlattice was grown and was composed of 2 sets ofdifferent layer thicknesses: 30/20 and 10/20 nm GaAs/Al_(x)Ga_(1-x)Aswidths, respectively. The 30/20 set consisted of 40 wire templates, andthe 10/20 set consisted of 20 wire templates. A third superlattice wasgrown and was composed of 1 set of 8/8 nm GaAs/Al_(x)Ga_(1-x)As widths,respectively, and consisted of 20 wire templates.

The first processing step to define the nanometer scale features in thesuperlattice is the selective removal of a small amount of one layer, asindicated in FIG. 2. Either GaAs or AlGaAs may be selectively etched,depending upon the etch chemicals used. For removal of AlGaAs, a dilutemixture of buffered HF acid (approx. 15 mL 6:1 buffered oxide etch to 50mL H₂0) is used to etch a trench roughly 30 nm deep. Selective etchingof the GaAs is achieved using etchants such as NH₄OH/H₂O₂/H₂O (5 ml:100mL:1000 mL for 30% concentrations), or diluted mixtures of HCl/H₂O orother acids (˜5 mL:100 mL). FIG. 4 a is a scanning electron microscope(SEM) image of the superlattice after a selective AlGaAs etch. TheAlGaAs layers appear dark, as they are at a lower elevation relative tothe brighter GaAs layers. The image shows only the 20/40, 10/20 and 5/15nm sets only. The topography of the etched layers is found by rotatingthe sample 90°, such that the surface profile is visible, as shown inFIG. 4 b. Here the contrast is reversed, as the dark rectangles seen arethe GaAs layers, and the depth of the AlGaAs trenches is easilyobserved. The high quality of the selective etch and the distinct,square profile of the GaAs layers shows the utility of this approach toprepare templates for nanometer scale devices.

We have also developed a chemo-mechanical processing method whichpermits the fabrication of superlattice areas as long as 10⁷ nm. Theselective chemical polishing of the material in the trenches and removalof the chemical reaction by product is achieved using a slurry of silicaparticles with sizes as small as 100 nm. The pH of the chemical solutionis chosen to remove preferentially GaAs in our case. However, another pHcan be chosen to remove preferentially the AlGaAs.

To prepare metallic wires, ˜30-150 Å of metal is evaporated onto theGaAs layers of the superlattice, tilted at 56° relative to horizontal.The precise angle at which the superlattice is tilted affects thethickness and shape of the deposited wires, and may be fine-tuned toachieve the desired properties. The thickness of the deposited metal canvary over a wide range, depending on the superlattice spacing anddesired wire width. The wire-coated superlattice is then placed on topof a ˜10 nm thick layer of epoxy, spun onto a suitable substrate such assilicon, silicon-on-insulator, silicon oxide, or other substrate theepoxy will adhere to. The epoxy is cured by heating to 135° C. for 30min, forming a strong bond to the metal on the superlattice. Finally,the wires were freed from the superlattice with a GaAs-oxide etch,either dilute HCl or Kl/I₂ solution.

Wires deposited with this technique are uniform and continuous over thelength of the GaAs superlattices (e.g. 2-3 mm), with nearly no defects.FIG. 5 a presents a SEM image of four sets of Pt wires with 50/60,30/50, 20/40, and 10/20 nm width/spacing. FIG. 5 b shows a highmagnification SEM image of 30/30 and 15/15 nm Pt wires, highlighting theprecision of this technique at small length scales. FIG. 5 c shows the8/8 nm width/spacing wires patterned using a different superlatticemaster. For both FIG. 5 b and FIG. 5 c, the wires are straight, nottouching, and show no visible defects over this entire span. The wireshave distinct sidewalls, sharp edges and flat tops, attributed to thewell-defined edges of the superlattice used to create these wires. Asidefrom gold wires, which are not structurally stable for long timeperiods, all of the metals examined are quite smooth and continuous.These characteristics are maintained for stretches greater than 100micrometers in most areas.

The process described above can also be utilized to form complexcircuitry on nanometer length scales by repetition. One such structureis the crossbar—two sets of overlapping wires oriented roughly 90° toeach other. These types of circuits are essential for memoryapplications, and can be exploited for logic gates as well. The benignconditions required for the art described here may allow application ofthis technique to molecular electronics and sensors as well asconventional metallic and semiconductor circuits. FIGS. 6 a and 6b showscanning electron microscopy (SEM) images of a set of Pt crossbars,demonstrating the large range of length scales possible. FIG. 6 a showsa crossbar made from two sets of 50/60, 30/50, 20/40, and 10/20 nm Ptwires, and the fidelity at all length scales. FIG. 6 b is amagnification of the 20/40-20/40 crossing, displaying the accuracy withwhich the circuits may be produced. If used to construct a memory, thesewires would produce a density of 300 gigabytes/cm², a hundred timesdenser than currently possible with semiconductor technology.

Poly-silicon or single crystalline silicon wires can also be made usingpost-processing, an example of wires that could not normally bedeposited with this method. First, a set of metal wires are depositedfrom the superlattice onto 50 nm of poly- or single crystal silicon,grown onto a silicon-dioxide substrate. Then a brief O₂-plasma etch isused to remove excess adhesive (epoxy in this case), followed by aCHF₃/O₂ plasma to etch the crystalline silicon layer underneath. Theprocess is outlined in the final step of FIG. 2. The precise etchconditions are not central to the processing, and may be altered. Thisetch step removes the silicon between the metal wires, but not underthem, effectively transferring the dimensions of the metallicsuperlattice wires to the silicon layer. Finally, the metal lines andepoxy are removed with a solution of concentrated 3 HCl:1 HNO₃, leavingonly the poly- or single crystalline silicon wires. A SEM image ofsingle crystal silicon wires made in this manner is shown in FIG. 7. Thewires are 20 nm wide, with 40 wires at 30 nm spacing (60 nm pitch), andanother 20 wires at 10 nm spacing (30 nm pitch). The attributes of thesewires are similar to those of the metal wires—they are smooth andcontinuous, show well-defined edges and no contact between wires. Thistype of processing is extremely promising for fabrication of manycrystalline semiconductor materials that cannot be directionallyevaporated.

A demonstration that these wires are robust to further semiconductingprocessing steps was carried out by preparing suspended Pt wires,designed to act as resonators. Pt wire resonators were fabricated byselectively undercutting the supporting substrate, thus suspending thewires over a trench, as shown in FIG. 8. Here, 20 nm Pt wires at 150 nmpitch were deposited using the SNAP technique onto a bare silicon wafer.The adhesive epoxy layer was removed with an O₂ reactive ion etch plasmatreatment. Poly(methylmethacrylate) (PMMA) electron beam resist was spuncoat on top of the Pt wires, and trenches of various widths werepatterned over the wires with electron beam lithography into PMMA. Theexposed Si substrate beneath the wires was selectively etched away withXeF₂ gas.

To replicate the SNAP process over an entire wafer or selected areas ofa wafer, the use of a stamping technique is preferred. FIG. 9illustrates two possible approaches which both use stamps developedusing the SNAP process.

In the first approach (FIG. 9 a) a photoresist or other organic thinlayer is embossed using the stamp and an adequate pressure. Ananti-adhesion coating of the stamp material insures that the embossedlayer does not stick to the stamp. In addition, a pattern transferredonto a rigid substrate via the SNAP process could also be used as thestamping master. This operation can then be repeated periodically on thedesired areas of a large wafer.

The second method shown in FIG. 9 b demonstrates the use of a stampfabricated with the SNAP process to create near-field optical exposureof a photo-sensitive material. First the stamp is brought in proximityor contact with a thin photoresist. A laser or other light source isthen used to expose the photoresist in near field optic conditions. Thenear field conditions insure that the resolution of the photoresistexposure is not limited by the wavelength of the light used. Afterdeveloping, the exposed photoresist can be used to pattern trenches,wires or other structures on any type of substrate.

Having thus described exemplary embodiments of the present invention, itshould be noted by those skilled in the art that the within disclosuresare exemplary only and that various other alternatives, adaptations andmodifications may be made within the scope of the present invention.Accordingly, the present invention is not limited to the above preferredembodiments and examples, but is only limited by the following claims.

REFERENCES

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1. A device comprising: a substrate that includes a surface; and aplurality of nanoscale wire bodies that each have a length, saidnanoscale wire bodies being located on the surface of said substrate ina parallel manner, said nanoscale wire bodies comprising: a base portionthat is attached to said substrate surface, said base portion having twoedges that extend along the length of said nanoscale wire body, said twoedges defining the width of said base portion; and one or more legportions that extend along the length of said nanoscale wire body andwhich extend away from the said substrate, said one or more leg portionsbeing located at one or both edges of said base portion.
 2. A deviceaccording to claim 1 wherein said leg portions extend from only one edgeof said base portion.
 3. A device according to claim 1 wherein the widthof said base portion is from about 2 nm to about 60 nanometers.
 4. Adevice according to claim 1, wherein the distance between the edges ofthe adjacent base portions is from 1 nm to 100 nm.
 5. A device accordingto claim 1, wherein said base portion is about 10 to 400 angstromsthick.
 6. A device according to claim 1 wherein said wire bodiescomprise material selected from the group consisting of metals,semiconductors, ceramics and organics.